1. Field of the Invention
The present invention relates generally to the design of semiconductor integrated circuits (ICs) or of electronic packages and, more particularly, to an efficient procedure for adding fill shapes to the design to correct for process deviations.
2. Description of the Prior Art
Semiconductor integrated circuits (ICs) and printed circuit packages are typically composed of layered structures. The layered structures may include several layers of conducting, insulating and/or combinations of other materials. The layers typically are structured in a horizontal dimension by fabrication processes, wherein the fabrication processes are used to transfer patterns defined in physical designs or layouts to the actual physical layers. The physical designs may be represented by computer data corresponding to two-dimensional shapes. The computer data may also be organized in a hierarchical data structure for exploiting the repetitive structure usually found in circuits and packages.
In some instances, the action of a fabrication process is affected by the specific design patterns being transferred to a layer of physical material. For example, a local pattern density of a design, i.e., the fraction of area over which material is deposited (or removed), can affect the shapes and dimensions of features being patterned in a particular layer. The amount and extent of the affected shapes and dimensions of features within a given area i.e., the "locality extent," is also dependent on the specific fabrication process being used. As a specific example, in a reactive ion etching (RIE) process step, a deficiency in a local pattern density may occur in which a surplus of material is to be etched away. The etching deficiency thus causes the pattern features to be too large (i.e., "under etched") wherein the deficiency occurred due to a depletion of the etchants during the etching process step. This surplus effect can appear to act at on a length scale of one hundred micrometers to millimeters (i.e. 0.1 to 1 mm). Other processes that may be adversely affected by local pattern density include lithographic patterning of resist materials and chemical-mechanical (so called "chem-mech") polishing (CMP).
There have been a variety of approaches to solving the above problem, some of which pertain to the fabrication process itself. Other solutions have included modifying the physical design to mitigate the pattern-dependent effects. The approach of the latter type solution is to reduce deviations from design to fabricated part. Such a reduction in the deviations is accomplished by adding fill shapes that have no electrical function but which reduce variations in a local pattern density. There are several drawbacks to this latter approach, however, including the possibility that the fill shapes may affect an electrical behavior/performance of the resultant device. The fill shapes are also difficult to add to a design manually and may be computationally costly to generate automatically. Furthermore, the fill shapes may significantly increase a data size of a physical design, thereby making subsequent data-handling steps (e.g., mask fracturing) more difficult.
In U.S. Pat. No. 5,278,105 entitled "Semiconductor Device With Dummy Features In Active Layers" to Eden et al., the use of fill shapes for correcting process problems due to local pattern density deficiencies is described. Briefly, Eden teaches a method of adding fill shapes to each active layer of a semiconductor device. A "virtual layer" is created by recording all active areas of an active layer. A guard band of a specified width is drawn around the active areas. A further guard band is drawn around all active regions of all layers to prevent line to line and interlayer parasitic capacitance. This procedure is repeated with all active layers, adding active regions and guard bands to the virtual layer for each layer. A blocking layer is also added to the virtual layer to block out user defined regions where fill shapes can not be added. Ultimately, the virtual layer defines the regions where fill shapes can not be added. Fill shapes are added outside of these regions for each active layer.
Eden, however, does not teach a method of generating any specific fill shapes. Nor does Eden disclose any suitable criteria of where to strategically add specific fill shapes in a design. Furthermore, as currently practiced in the industry, fill shapes are added based on the average pattern density for an entire chip. While this helps to lower the variations in pattern density within a chip and from chip to chip, it can not fully accommodate the wide range of within-chip pattern density variation. Furthermore, adding fill shapes based on an average pattern density of the entire chip is too coarse-grained to provide a tight pattern density control from chip to chip.
Consequently, it would be desirable to have a method for calculating a fill pattern and generating fill shapes for a design, and further for achieving a particular target density value for a chip or a specific area of a chip.